It is desirable in semiconductor construction to reduce the area and volume of devices on the chip, i.e., N-channel MOSFETS, P-channel MOSFETS, storage capacitors, etc. Methods to reduce size include providing narrower channel areas, narrower conducting metal lines, stacked components, etc. There are certain problems that occur in downsizing, i.e., short channel characteristics where there is a subthreshold V.sub.t current leakage or shifting of V.sub.t with age, higher contact resistances, "hot electron" problems, ion diffusion in the FET channel area, additional masking steps, etc.
Raised source/drains are not new art since there are methods of forming the raised source/drain by selective epitaxial growth, over the source/drain areas, of silicon or polysilicon. This more expensive process also can create phosphorous ion diffusion problems in the channel areas under the transistor gate. It is the purpose of this invention to offer the following advantages:
eliminate a high-current source/drain ion implant step following formation of an oxide spacer; PA1 improve an N-channel MOSFET transistor subthreshold current characteristic; PA1 avoid the need for additional source/drain definition masking steps, such as N- and P-implants; PA1 reduce the outdiffusion of phosphorous ions in the channel area; PA1 reduce the source and drain junction contact resistance; and PA1 provide a simpler raised source/drain process that can be integrated with a capacitor or P-channel fabrication process. PA1 growing a second field oxide layer over the source and drain areas; PA1 selectively etching the silicon nitride barrier spacers, thereby exposing a narrow source and drain area between the oxide spacer and the second field oxide layer; PA1 depositing a titanium nitride layer over the MOSFET device; PA1 depositing a polysilicon layer over the titanium nitride layer; PA1 and simultaneously doping the polysilicon layer to create a conducting polysilicon layer, wherein the titanium nitride layer acts as a barrier to ion migration to the source and drain areas; PA1 etching the polysilicon layer to form an opening over the gate structure and a boundary over the field oxide layer wherein the titanium nitride acts as an etch barrier; PA1 etching the titanium nitride layer to form openings over the gate structure and a boundary over the field oxide layer thereby forming a raised source/drain electrical connection; PA1 depositing an oxide isolation layer over the MOSFET device; PA1 patterning a pair of contact openings in the oxide isolation layer over the conducting polysilicon wherein the titanium nitride acts as an etch barrier; PA1 depositing a thin titanium nitride layer within the contact openings; PA1 depositing and patterning a metal conductor within the contact opening; and then PA1 depositing and patterning a pair of bit line metal conductors over the metal conductor in the contact opening thereby providing a low-resistance electrical connection from the bit line through the raised source/drain electrical connection to the narrow source and drain areas. PA1 depositing sequentially over the semiconductor substrate, a thin gate oxide layer, a polysilicon layer, a refractory metal silicide layer, and a top layer oxide; PA1 patterning a gate structure over an N-channel area; PA1 implanting ions in a source and drain area adjacent the N-channel gate structure; PA1 patterning a barrier spacer on opposite sides of the N-channel gate structure; PA1 growing a field oxide adjacent the N-channel gate structure over the substrate wherein the field oxide is bounded by the barrier spacer; PA1 etching to selectively remove the barrier spacer thereby exposing the source and drain areas; PA1 depositing a photoresist layer over the N-channel and P-channel devises; PA1 patterning a P-channel gate structure while protecting the N-channel device with the photoresist layer; PA1 ion implanting a low-dose P-channel source and drain area; PA1 forming an oxide spacer on opposite sides of the N-channel and P-channel gate structures; PA1 depositing a titanium nitride layer over the N-channel and P-channel devices; PA1 depositing a polysilicon layer over the N-channel and P-channel devises; PA1 in situ doping the polysilicon layer to create a conducting polysilicon layer; PA1 selectively etching the conducting polysilicon layer over the N-channel and P-channel devices to form an opening over the N-channel and P-channel gate structures and a boundary over the field oxide layer of the N-channel and P-channel devices; PA1 selectively etching the titanium nitride layer to form openings over the N-channel and P-channel gate structures and a boundary over the field oxide layers thereby forming a raised source/drain electrical connection at the N-channel and P-channel devices; PA1 depositing an oxide isolation layer over the MOSFET device; PA1 patterning a plurality of contact openings in the oxide isolation layer over the conducting polysilicon of the N-channel and P-channel devices; PA1 depositing a thin titanium nitride layer within the contact openings; PA1 depositing and patterning a tungsten conductor within the plurality contact openings; and then PA1 depositing and patterning a plurality of bit line metal conductors over the metal conductor in the contact opening thereby providing a low-resistance electrical connection from the bit line through the raised source/drain electrical connection to the source and drain areas of both N-channel and P-channel devices. PA1 depositing and in situ doping a polysilicon layer over the TiN layer, wherein the TiN layer acts as a barrier to dopant atoms; PA1 simultaneously, patterning a pair of transistor raised source/drain electrical connections and a pair of capacitor storage node plates on the titanium nitride and polysilicon layers; PA1 depositing a thin dielectric over the capacitor storage node plates; PA1 depositing and patterning a pair of capacitor top plates over the dielectric and storage node plates; PA1 depositing an oxide isolation layer; PA1 patterning contact openings in the oxide isolation layer over the top capacitor plates; PA1 depositing and patterning a connection to the capacitor top plates at the end of the arrays to a ##EQU1## potential; depositing and patterning a metal bit line electrical conductor connecting the transistor source areas and the raised source/drain electrical connection thereby connecting the pair of N-channel MOSFET transistors to the pair of capacitor memory cells. PA1 depositing a titanium nitride (TiN) layer by a CVD process over the N-channel and P-channel transistors, and the gate oxide areas; PA1 depositing and in situ doping a polysilicon layer over the TiN layer, wherein the TiN layer acts as a barrier to dopant atoms; PA1 simultaneously patterning a raised source/ drain electrical connection on each transistor and a pair of capacitor storage node plates on the titanium nitride and polysilicon layers; PA1 depositing a thin dielectric over the capacitor storage node plates; PA1 depositing and patterning a pair of capacitor top plates over the dielectric and storage node plates; PA1 depositing an oxide isolation layer; PA1 patterning contact openings in the oxide isolation layer over the top capacitor plates; PA1 depositing and patterning a connection to the capacitor top plates at the end of an array to a ##EQU2## potential; and then depositing and patterning a metal bit line electric conductor connecting the transistor source areas to the bit line thereby forming a pair of N-channel MOSFET transistors and a pair of capacitor memory cells and a P-channel MOSFET transistor.